1. Field of the Invention
This invention relates to semiconductor die packaging, and more particularly to a dual-dies packaging structure, and a packaging method.
2. Description of Related Art
As a device integration continuously increases, a more efficient packaging structure of dies is also desired by manufacturers. In order to more effectively use an available space, two dies may be packaged together in an integrated circuit (IC) chip, in which these two dies may have either similar function or different function. Thus, the dual-dies IC chip can have a greater capability or more various functions. However, it is difficult to achieve this kind of dual-dies packaging structure.
When two dies are to be packaged together, these two dies usually are respectively mounted on both sides of a lead frame. If these two dies have an identical circuit layout, such as two dynamic random access memory (DRAM) dies to increase memory capacity, those bonding wires between bonding pads and the lead frame inevitably need to cross to each other or even entangle together. In order to avoid this issue, several dual-dies packaging structures are proposed.
FIG. 1 is a cross-sectional view of an IC chip, schematically illustrating a conventional dual-dies packaging structure. In FIG. 1, an usual dual-dies packaging structure includes a die pad 14, which is horizontally set. A die 12 is fixed on an upper surface of the die pad 14, and a die 16 is fixed on a lower surface of the die pad 14. The die 16 is a mirror die with respect to the die 12 so that bonding wires 10 are not necessarily crossed to each other. In this conventional manner, the circuit layout of the die 16 is necessary to be extra designed to fit its mirror structure with respect to the die 12. This increases fabrication time and fabrication cost.
FIG. 2 is a cross-sectional view of an IC chip, schematically illustrating an another conventional dual-dies packaging structure. In FIG. 2, a die pad 33 is horizontally set in a space. According to the geometry location of the die pad 33, the die pad 33 includes an additional circuit, called an interposer 36, located on a lower surface of the die pad 33. An usual die 32 is fixed on an upper surface of the die pad 33, a die 34, identical to the die 32, is fixed on a lower surface of the die pad 33. The interposer 36 is used to convert bonding pad locations of the die 34 into a new locations so that bonding wires 30 for the die 34 need not cross each other. This conventional method has it limitation. If a die dimension is large and occupies most of the area of the die pad 33, then there is no available area on the die pad 33 for forming the interposer 36. Moreover signal is led out through the interposer 36, the signal may be distorted. An unequal bonding length may also cause a signal delay.
There is also another dual-dies packaging structure. A die pad is replaced by a printed circuit board. Through a layout of the printed circuit board, signals of dies can be led out. This method also has it drawbacks. Since the material of the printed circuit board and the packaging glue have a poor glue performance. This cause an increase of fabrication cost to obtain a sufficient glue strength. Moreover, the signals may also distorted.